As a result of rapid advances in semiconductor technology, Very Large Scale Integrated Circuits (VLSIs) which are much larger in scale and more complicated than Large Scale Integrated Circuits (LSIs), and which exhibit superior performance, have already made their appearance, and Ultra Large Scale Integrated Circuits (ULSIs) are soon expected. As a result, serious problems arise with regard to the type of tests that will be required for the chips.
With conventional LSI chips, testing is normally performed with an LSI tester, using only the functions which are defined for use in normal operations, but with VLSIs and ULSIs it has become necessary to provide an expanded volume of test vectors. Also, LSI testers which can cope with tests for these chips require higher and higher performance and therefore cost more.
In addition, it is necessary to consider performing still further tests to test the chip to an adequate degree. For this reason, considerable cost must be incurred for a Central Processing Unit (CPU). The complete testing of VLSI and ULSI chips by conventional means is therefore almost impossible in practice. In order to solve such a serious problem, a test circuit is incorporated in the chip in advance for easy testing, and much attention is being paid to testability and cost. A built-in self test (hereinafter BIST), uses one type of design for testability comprising a test signal generating circuit for a circuit device under test (hereinafter we call it "DUT"). A test result evaluation circuit is built into the LSI chip. The test is initiated by an external signal. After the test is completed, signals indicating that the DUT is judged to be good or not good, or data indicating the test result are output. Because an LSI tester is usually not required, test costs are very effectively reduced. Furthermore, the test can be performed under the same conditions in which the chip is used in practice so that testing is possible after the chip has been installed. Because of these many conspicuous advantages, it is expected that the BIST will play an extremely important role in testing VLSIs and ULSIs.
In the above-mentioned type of BIST, the most basic technology is known as signature analysis. This technology is based on a linear feedback shift register (hereinafter LFSR), which will now be explained. An LFSR (n bits in width) can be used as both a test signal generating circuit and a test result evaluation circuit. An LFSR as a test signal generating circuit, as illustrated in FIG. 1A (where n=8), is a simple register circuit comprising n D-type flip-flops 31 connected in series and a feedback circuit 32 for creating an exclusive OR (hereinafter XOR) of outputs Q of specific flip-flops 31 and inputting the XOR output to the D-input of the first of the serially-connected flip-flops 31.
When activated by the setting of an initial value other than all-Os in the flip-flops 31-0 to 31-7 (the circuit for initializing the LFSR has been omitted from the drawings), (2.sup.n -1) items of pseudo-random data are output, repeated in a set order. Serial output is possible if any of the pseudo-random data outputs from the n flip-flops 31 is utilized, and, in addition, parallel output is possible if some or all of these outputs are utilized. With recent VLSIs or ULSIs for data processing of many bit widths, the latter method is normal and important.
Signature analysis is the technology using an LFSR as a test result evaluation circuit. In this case, a serial-input type LFSR to which the output from a DUT is input serially, and a parallel-input type LFSR, referred to as a multiple input signature register (MISR), are also used.
However, with a VLSI or ULSI the latter method is, of course, exceedingly important. Accordingly, this explanation will be restricted to this type of LFSR.
An example of the configuration of an n-bit parallel input type of LFSR is shown in FIG. 1B (for n=8). The Q output of a bit i (i=0, . . . , 6) of the flip-flops 33 in the LFSR and external data (Ini+1) of the bit i+1 are input to a D input of a bit (i+1) of the flip-flop 33 through an attached XOR circuit 34. In addition, the output of the feedback circuit 32 of the previously described LFSR and the external data of the bit 0 are input through the XOR circuit 34 to the D input of a bit 0 of the flip-flop 33.
With this configuration, when the response output from the DUT are sequentially applied to the LFSR in which at first a certain known value is stored, pseudo-random data are formed in the internal flip-flops of the LFSR corresponding to these values, and finally, certain inherent test result data are formed in the LFSR. The data created in the LFSR are referred to as a signature, and the operation by which the response output from the DUT is applied and the signature created is referred to as a signature compression.
Signature analysis is an analytical method wherein the response output from the DUT is signature-compressed for a sequence of test data; and, finally, the DUT is evaluated as good or not good by comparing the test results (signature) remaining in the LFSR with the expected value only once.
In general, after signature compression is executed with a sufficient number of test data, the reliability, that a signature indicating the DUT to be fault-free is really true, is calculated by subtracting an "aliasing" probability which is equal to that of a faulty DUT outputting the same signature as that of a fault-free DUT from 1, and the "Aliasing" probability is 2.sup.-n which can normally be ignored if n is large (n&gt;24). Therefore, with a VLSI or ULSI which normally processes data of many bits in width (n.gtoreq.32), the reliability of signature analysis is extremely high. Furthermore, although the above-mentioned LFSR is provided exclusively with a BIST, it is also often used as a register for normal operation, resulting in an economy in test circuitry. However, there are also problems associated with this type of BIST. The most important of these is the reverse of the merits of the BIST. After execution of the BIST, because basically only one piece of test result data remains in which the response data from the DUT is signature compressed for much test data, it is possible only to detect the occurrence of erroneous or wrong outputs during the BIST. Because it is not possible to know the cycle or time of the output data when erroneous outputs occur, it is not easy to diagnose an erroneous output to specify the location of the corresponding fault in the DUT. As the simplest and most effective method of solving this problem, a feedback loop for an exclusive OR of the LFSR is isolated in a suitable test mode and included in the data route (referred to as the scan chain) in which the serial-connected section of the flip-flops which comprise the LFSR is connected to an external part of the chip so that the contents can be read out serially (referred to as scan transmission).
Furthermore, when data is set to a certain data in the LFSR, the BIST can be initialized. (This initialization can also be performed in series by means of a scan operation). In this manner, four types of operations, specifically, normal operation, signature compression, scanning operations, and fixed data setting operation, are possible in a register circuit used as a BIST. This is extremely important in providing a BIST for overcoming the weak points in fault diagnosis. A representative example of a register for a BIST with the technology outlined above is a BILBO (built-in logic block observer).
This BILBO is illustrated in FIG. 2 (8-bit width). The operation of this circuit is determined by two mode signals B1 and 2. When B1=1 and B2=1, normal operation is carried out (each output Z1 to Z8 from the DUT is stored in separate D-type flip-flops 41) (FIG. 3A); and when B1=1 and B2=0, each flip-flop 41 operates as a parallel input LFSR (FIG. 3C), and parallel signature compression is possible. In addition, when B1 =0 and B2=0, each flip-flop 41 becomes a shift register which can perform a scan operation (FIG. 3B). Further, although not shown in the drawings, when B1=0 and B2=1, fixed data setting (reset) is possible.
In the BILBO method outlined above, a BIST register containing a BIST with a simple structure which overcomes the weak points in the above-mentioned fault diagnosis is provided. However, in the BILBO method, in order to provide a scan operation (and fixed data setting), it is necessary to insert an AND circuit 43 between the output of the DUT and the flip-flop inside the LFSR, in addition to an indispensable exclusive OR circuit 42 for signature compression, and there is a major drawback in that the performance is degraded during normal operation. The countermeasures for the drawbacks of this BILBO method, restricted to the case where the DUT has a ratio type or a precharged type output, are comparatively simple.
Specifically, as illustrated in a ratio-type ROM 51 as shown in FIG. 4, there is a connection between each output and the ground potential, and the elements are turned ON and OFF by means of a common signal. A scan operation and the setting of initial values can be provided by turning the elements ON without the insertion of an AND circuit.
In FIG. 4, the reference numeral 53 designates a word line, the reference numeral 54 a bit line, and the reference numeral 52 a load circuit for the bit line, comprising a PMOS element which is normally ON. The data in a ROM 51 is determined by whether an NMOS element 55 is positioned (logic 0) or not (logic 1) at the point where the bit line 54 and the word line 53 intersect. In addition, the reference letter A designates the above-mentioned common signal, and the reference numeral 56 designates an NMOS element which is turned ON or OFF by the signal A.
As can be clearly understood from FIG. 4, when the common signal A is set at "1", the output of the bit line 54 is mandatorily set to logic "0". Therefore, a scan operation (when B=1) or fixed data setting (when B=0) is provided according to the value of the signal B (A=0 and B=0 gives normal operation; A=0 and B=1 gives parallel signature compression), and the AND circuit becomes unnecessary as far as the BILBO is concerned.
However, for the above-mentioned type of countermeasure to be possible, the output of the DUT must, strictly speaking, be the ratio type or the precharged type. A solution is not obtained in the case of a more common output.
On the other hand, there is a conventional semiconductor circuit device in which a built-in test circuit with improved operational speed is disclosed for the conventional semiconductor integrated circuit device for which a selector circuit S1 to S5 is provided for which the output Q1 to Q5 of an external input line I1 to I5 and a D-type flip-flop circuit F1 to F5 becomes the input.
A fed-through mode passed through a register section is operated by outputting the external input via the selector circuit.
However, even with this type of test circuit, an AND circuit which is required for the scan operation is utilized in the same manner as the BILBO method shown in FIG. 2, together with the exclusive OR circuit required in signature compression.
As outlined above, in a conventional BILBO it is necessary to insert an AND circuit into the data route from the output of a DUT to a data input terminal D for a flip-flop comprising an LFSR, in addition to an indispensable XOR circuit for signature compression, for a scan operation.
Accordingly, operating speed during normal operation drops; and performance drops because data obtained from the DUT is set in the flip-flop through the XOR circuit and the AND circuit.